1. Field
Embodiments described herein generally relate to processes for forming silicon fins in a FinFET structure. More specifically, embodiments described herein relate to trimming silicon fin width through oxidation and etch.
2. Description of the Related Art
In response to an increased need for smaller electronic devices with denser circuits, devices with three dimensional (3D) structures have been developed. An example of such devices may include FinFETs having conductive fin-like structures that are raised vertically above a horizontally extending substrate. Conventional FinFETs may be formed on a substrate, such as a semiconducting substrate or silicon-on-insulator. The substrate may comprise a semiconducting substrate and an oxide layer disposed on the semiconducting substrate.
When manufacturing FinFETs, it is desirable to have a fin structure with a high aspect ratio. A higher aspect ratio for the fin structure allows a larger amount of current to be provided through the same amount of topographical area. Fabrication of high aspect ratio FinFETs is difficult as a result of the reduced critical dimensions required for sub-10 nm nodes. The reduced critical dimensions create challenges in forming trenches, fins and other features which are required to form FinFETs.
Thus, there is a need in the art for improved methods of forming sub-10 nm node FinFETs.